? semiconductor components industries, llc, 2014 february , 2014 ? rev . 1 1 publication order number: AND9071/d AND9071/d noise management in motor drives with igbt s introduction the introduction of igbt s has enabled motor drives to move to higher switching frequencies and hence, more compact implementations. however , a side product of these advances is the increased vulnerability to the emi/noise issues. the emi/emc management has always been a challenging aspect of any motor drive design and development, with a significant amount of time spent in finding empirical solutions to problems that manifest themselves during the development. the introduction of igbt s switching at higher frequencies may complicate this task due to (a) higher switching frequencies and (b) increased proximity between components/subsystems of fered by the higher level of compactness. however , as many practicing engineers recognize, techniques exist to address emi issues ef fectively . a number of these techniques are discussed in this section. t h e focus is on building preventive solutions into the design a n d layout rather than dealing with them through debugging and redesign. a typical block diagram of the motor drive circuit is shown in figure 1 and will be used to illustrate various techniques for emi management. motor igbt based inverter front-end smps (ac-dc converter) igbt drivers digital controller (uc, dsp or other) ac input dc link sensors figure 1. typical motor drive system block diagram http://onsemi.com application note http://
AND9071/d http://onsemi.com 2 as shown in this block diagram, the motor drive system contains blocks that process high power as well as those that process low level signals. sensitivity of these blocks to emi does dif fer and when they are colocated, it is important to minimize the interactions between the two types. in general, the following areas of emi management can be identified: 1. ensuring that digital controller circuits do not get perturbed by the high power switching noise in the inverter or the ac-dc converter . 2. ensuring that the integrity of the sensed signals from the motor is not compromised due to the emi generated in other blocks. 3. ensuring that the power blocks do not get into false switching states due to presence of parasitic switching noise. 4. ensuring that the driver (which is an interface block) acts as a proper buf fer between low power circuits and high power circuits. 5. ensuring that the motor drive circuit as a whole does not emit or conduct interference signals beyond the limits specified in the emi/emc compliance requirements. the first four items above are necessary for acceptable and robust functioning of the motor drive systems, while t h e last one is clearly for meeting the external agency compliance requirements. the techniques for noise management include better circuit design, relevant component choices and proper layout. each of these will be addressed in the following sections. circuit techniques circuit design ca n have a profound influence on both the amount of noise produced and the susceptibility of motor drive circuits to the noisy environments in which they operate. front-end smps when looking at the front-end ac-dc smps, it is important to minimize its contribution to the ambient noise. this can be done by using soft-switching techniques or at the very least, using ef fective snubbers to minimize the radiated emi. any high di/dt or dv/dt in the smps can lead to malfunction of more sensitive adjacent blocks such as controller , driver or sensor . figure 2. t ypical igbt -based inverter stage (one phase) hv rail pwmh pwml return pgnd phase d2 d1 ls dr v hs dr v level shift q2 q1 c d pgnd inverter and driver when considering the inverter and driver blocks, igbt s are typically used in the high voltage applications only . in these applications, the inverter consists of three identical dual n-channel stages (each phase consisting of one high-side igbt and one low-side igbt , anti-parallel diodes for each and associated drive circuitry as shown in figure 2). here, the challenge is to provide the level shifting for the high-side igbt drive. the options for the drive circuit include: ? low side discrete/integrated drivers followed by gate drive transformers ? this option allows the gate drive transformer to provide the required level shifting for high-side igbt , while the low side is coupled directly
AND9071/d http://onsemi.com 3 to the driver . needs adequate delay matching and timing management to control the turn-on and turn-of f of the two igbt s. noise susceptibility is limited with correct gate drive transformer design which would minimize the capacitance between the windings and may also require a shield. ? use of integrated high-side, low-side driver with internal timing management ? this option integrates the drive circuit into a single ic. although the early versions of such drivers gained some notoriety due to their noise susceptibility and also noise radiation, subsequent versions have incorporated better layout and control to overcome the noise issues. ? use of optocouplers to transmit the gate drive signal from controller and use of local drivers for each igbt ? this option provides the best decoupling between the power and control stages. however , it comes with the price of requiring special bias and drive circuits and the need for high speed optocouplers. while the choice amongst these options depends on the designer familiarity , bom budget constraints and power levels, it is safe to say that good design and layout practices will allow successful implementation of any of these options in the motor drive applications. sensor the sensor block can also benefit from common design practices such as filtering and buf fering to improve noise immunity . i n general, the sensor signals have time constants an order of magnitude below the one seen in the pwm inverter , s o i t i s easy to eliminate the noise coupling through good low pass filtering techniques followed by use of schmitt trigger gates to provide additional noise immunity . this is illustrated in figure 3. the hall sensors are in a typically noisy environment since they are close to motor windings with their pwm noise. in order to isolate the sensed position signal from the noise picked up by the hall sensors before it reaches the controller , filtering and buf fering are used. the filter consisting of r2, r3 and c2, has a time constant of 100 ns ? much lower than the hall sensor response times which are typically in micro-seconds. this is good enough to filter out the high-frequency noise spikes, while not disturbing the sensed signal. the filtered signal is next fed to a gate with a schmitt trigger that has a relatively slow response time and built-in hysteresis. the digitization ef fect of fered by the schmitt trigger allows the sensed signal to be fed into the controller in a relatively noise-free manner . to controller or dsp figure 3. processing of hall sensor input for low noise immunity +5 v r3 r2 22 22 hall sensor r1 1 k c2 470 pf mc14584 c1 0.1 f controller finally , the controller , which may be the most noise sensitive block, also requires special attention. it needs good bypassing of critical inputs and buf fering of the outputs. the immunity of the controller to noise can be further improved by firmware control where the code provides additional protection against random sequencing of drive signals caused by noise.
AND9071/d http://onsemi.com 4 component choices in addition to good circuit design techniques, appropriate component choices play an important role in emi mitigation. major component groups in a motor drive system are addressed in this section. power semiconductors switching elements such as igbt s and mosfet s act as source of emi and also exhibit susceptibility to it under certain conditions. t o address susceptibility , it is important to choose devices which have reasonably high threshold voltages to prevent noise spikes from turning them on spuriously . good, low impedance drive circuits are also important t o prevent faulty turn-on of the switching devices. while the noise emissions from switching devices are strictly a function of the switching speeds and can be controlled by shaping the switching intervals through the drive circuit, the built-in body diode of the mosfet is often a major contributor to emi. in motor drive applications, since the bidirectional switch currents are a norm, this phenomenon is more of a factor . here, igbt s provide a better alternative, since they do not have a body diode and an external anti-parallel diode can be independently chosen to meet the system requirements. t ypically , a soft recovery diode (with low qrr) is chosen. the reverse recovery of the high voltage diodes is also a concern in the high side drive circuits, where a high voltage diode is used to bootstrap the bias voltage for the floating high-side bias voltage. in many integrated drivers, this diode is built-in with very snappy turn-of f behavior and this leads to radiated emi issues. controllers and drivers (ics) since the controllers provide the required drive signals for the switching devices, it is important to build noise immunity in these devices. some controllers (both digital and analog) are inherently more noise immune than others. however , this fact is rarely acknowledged in public domain and it requires careful perusal of datasheets and/or application notes of a particular controller and/or prior experience designing with it to understand its vulnerability to emi. in controllers and drivers designed for better noise immunity , following features are generally observed: ? physical separation of power related pins and low level signals which may be noise sensitive ? suf ficient hysteresis on any comparator inputs ? separate analog and power ground pins ? signal thresholds which are not too low so that noise can trigger them ? specified noise immunity on critical pins (50 v/ns or better) ? ability to withstand negative transient for short duration without latching up the vulnerability can be minimized by good layout and bypassing practices and the pr oduct documentation usually provide guidance to the user regarding these practices. drivers are meant to be buf fers between the vulnerable control circuits and high-noise switching devices. however , in the absence of good design and layout practices, they c a n inadvertently become the conduits for the noise coupling. similar to the controllers, the ic drivers vary widely with regards t o t h e i r emi generation and susceptibility behavior . magnetics the choices for power magnetics, emi filter and noise filtering can have a significant impact on the system emi performance. often, the characterization of the magnetic components i s not as extensive as other components, leading to uninformed and faulty choices of magnetics in circuits. w ith respect to emi, it is important to recognize that all inductors have a self-resonant frequency (srf) beyond which they cease to be inductors. since the function of the inductor is to typically provide a high impedance at a specified frequency , the srf is a very critical parameter . the dc resistance of inductors provides damping which is good from an emi point of view , but adds to the power losses. also, depending on which section of the circuit the inductor is used in, the type of inductor may dif fer in terms of core material (ferrite, powder -iron etc.) and geometries (rod, toroid, ee cores etc.). the transformers used in the front-end smps also play a big role in emi generation if not properly designed. emi shields are often used to reduce the radiated emi and y-caps from primary to secondary are employed t o provide low impedance path for common mode noise. ferrite beads provide the quickest ?band-aid? solution to the emi problems during debugging stages, as they can be inserted easily (generally without altering the layout) and are ef fective i n slowing down the fast edges that cause emi. however , overreliance on these beads is not a good practice because (a) they invariably add to the losses and (b) they are not mechanically robust. other passives capacitors are extensively used for bypassing, while a judicious combination of resistors and capacitors is used for passive snubber implementations. the choice of capacitors is important because the esr values can impact the high frequency performance of capacitors adversely . in general, an smt ceramic cap is the best choice for bypass filtering. ceramic capacitors have very low esr and an smt package eliminates the lead inductance. the capacitor should b e connected as closely as possible to the leads of the chip that it is bypassing. t ypically a bypass capacitor is in the capacitance range of 0.01 f to 1 f. la yout
AND9071/d http://onsemi.com 5 i n a motor drive, layout is a critical part of the total design. often, getting a system to work properly is actually more a matter of layout than circuit design. the following discussion covers some general layout principals, power stage layouts, and controller layouts. it is realized by practicing engineers that there is no single ?correct? layout for an application. a good layout generally involves making a number of on the spot technical trade-of fs that cumulatively lead to better system performance. general principles: there are several general layout principles that are important to motor drive design. they can be described as five rules: rule 1 : minimize loop areas. a loop is the circuit trace path from the source of a signal (e.g. driver , fb node) to its destination (e.g. igbt , error amp) and back to its source through the return path. this is a general principle that applies to both power stages and noise sensitive inputs. loops are antennas. at noise sensitive inputs, the area enclosed by an incoming signal path and its return is proportional to the amount of noise picked up by the input. a t power stage outputs, the amount of noise that is radiated is also proportional to loop area. a corollary of this rule is that the placement of key components that are connected is very critical and they should be placed as close to each other as possible. rule 2 : cancel fields by running equal currents that flow in opposite directions as close as possible to each other . if t w o equal currents flow in opposite directions, the resulting electromagnetic fields will cancel as the two currents are brought infinitely close together . in printed circuit board layout, this situation can be approximated by running signals a n d their returns along the same path but on dif ferent layers. field cancellation is not perfect due to the finite physical separation, but is suf ficient to warrant serious attention in motor drive layouts. looked at from a dif ferent perspective, this is another way of looking at rule 1, i.e. minimize loop areas. rule 3: on traces that carry high speed signals avoid 90 degree angles, including ?t? connections. if you think of high speed signals in terms of wavefronts moving down a trace, the reason for avoiding 90 degree angles is straightforward. t o a high speed wavefront, a 90 degree angle i s a discontinuity that produces unwanted reflections. from a practical point of view , 90 degree turns on a single trace are easy to avoid by using two 45 degree angles or a curve. where two traces come together to form a ?t? connection, adding some copper pour to cut across the right angles accomplishes the same thing. rule 4 : connect signal circuit grounds to power grounds at only one point. the reason for this constraint is that transient voltage drops along power grounds can be substantial, due to high values of di/dt flowing through finite inductance. if signal processing circuit returns are connected to power ground a multiple points, then these transients will show up as return voltage dif ferences at dif ferent points in the signal processing circuitry . since signal processing circuitry seldom has the noise immunity to handle power ground transients, it is generally necessary to tie the signal ground t o the power ground at only one point. this rule can also be extended to use of ground planes. for power circuits, it is important to have either separate ground planes or ensure that the high current path on the ground plane does not traverse through sensitive signal ground areas on the same plane. rule 5: use v ias very sparingly and selectively . although vias of fer an easy routing solution for complex/dense pcbs, injudicious use of them could lead to emi and other problems. v ias are used primarily for 3 purposes: 1. t o provide signal connection to/from an inner layer plane such as ground plane as well as to provide signal connection between components places on separate layers. 2. t o provide alternative routing path for a trace when routing is not possible on the same layer due to presence of other higher priority traces. 3. t o provide thermal relief for high current carrying paths/planes on the inner layers. however , insertion of vias reduces the area of a plane or copper pour , adds capacitance between the vias and the adjoining signals on all layers and causes diversion in traces which could have been more directly routed. thus, addition o f vias involves trade-of fs that can be made by experienced layout designers and circuit designers together during the layout. layout consideration for power stage: there are two overriding objectives with regard to power stage layout. first, it is necessary to control noise a t the gate drives so power devices are not turned on when they are supposed to be of f or vice versa. second, it is highly desirable t o minimize radiated noise with layout, where tight loops and field cancellation can reduce the cost of filters and enclosures. looking first at the gate drive, noise management is greatly facilitated by using the source or emitter connection for each power device as a miniature ground plane for that device? s gate drive. this is particularly important for high side n-channel gate drives, where the gate drivers have high dv/dt displacements with respect to power ground. if the power device? s source or emitter connection is used like a ground plane, parasitic capacitive coupling back to power ground is minimized, thereby increasing the dv/dt immunity of the gate drive. t o illustrate this point, let? s refer to and assume that the high-side phase output swings 300 v i n 1 0 0 nsec as a result of a switching transition, and that the parasitic capacitance t o power ground, cp, is only 1 p f . then a simple i = c(dv/dt) calculation suggests that 3 ma of char ging current will flow through cp. this 3 ma into 5.6 k of node impedance is much more than enough to cause false transitions. these numbers illustrate a very high sensitivity to parasitic
AND9071/d http://onsemi.com 6 coupling, which makes layout o f this part of the circuit very important. in addition to viewing source or emitter connections as miniature ground planes, it is also important to keep any signals referenced to ground away from high side gate driver inputs. gate drive noise immunity is also facilitated by minimizing the loop area that contains the gate drive decoupling capacitor , gate driver , gate, and source or emitter of the power device. one way to do this is to route the gate drive signal either directly above or beneath its return. if the return is relatively wide (2.5 mm or greater) it forms the miniature ground plane that was previously discussed. the resulting minimum loop area minimizes capacitive coupling as well as antenna ef fects that inject noise at the input of the gate driver . in addition, relatively high peak gate drive currents get some field cancellation, which reduces radiated noise. the other major source of gate drive noise that causes false transitions is non-zero voltage drops in power grounds. using opto couplers and routing each gate drive return directly to the emitter of its corresponding power device is one of the ways to provide noise immunity . for motor drives where opto couplers are not practical, taking care to minimize the inductance between power device emitters or sources is a viable alternative. in terms of reducing the amount of noise that is produced by power stages, minimizing loop areas is a key consideration. the most important is the loop that includes the upper half-bridge igbt drain, lower half-bridge igbt source, and high frequency bus decoupling cap. the idea here is to try to keep the high di/dt that is produced during diode reverse recovery in as small an area as possible. this is a part of the circuit where running traces that have equal but opposite currents directly over each other is a priority . since the currents into and out of the decoupling cap are equal and opposite, running these two traces directly over each other provides field cancellation and minimum loop areas where they are needed most. figure 4 illustrates the dif ference between a loop that has been routed correctly and one that has not. in this figure, the solid circles represent pads, the schematic symbols show the components that are connected to the pads, and two routing layers are shown with cross-hatching that goes in opposite directions. note that by routing the two traces one over the other that the critical loop area is minimized. for similar reasons it is desirable to run power and return traces one directly on top of the other . in addition, if a current sensing resistor is used in the return, using a surface mount resistor is preferable due to its lower inductance. it also can be placed directly over the power trace, providing uninterrupted field cancellation from placing power and return traces over each other . again for field cancellation, it is also desirable to run phase outputs parallel and as close as possible to each other . figure 4. minimizing loop areas ???????? ???????? ???????? ???????? ???????? ???????? ??? ??? legend pa d t o p trace bott om trace avoid good practice
AND9071/d http://onsemi.com 7 the power stage is the place where avoiding right angles is most important. single traces are easy , two forty five degree angles or a curve easily accomplish a 90 degree turn. it is just as important to avoid 90 degree angles in t connections. illustrates correct versus incorrect routing for both cases. figure 5. routing to a void 90 degree angles single trace t connection avoid good practice a void good practice layout considerations for controllers: the primary layout issue with controllers is ground partitioning. a good place to start is with the architecture that is shown in figure 6. this architecture has several key attributes. analog ground and power ground are both separate and distinct from digital ground, and both contact digital ground at only one point. for the analog ground, it is preferable to make the one point as close as possible to the digital converter ? s ground reference (vrefl). the power ground the connection should be as close as possible to the microcomputer ? s power supply return (vss). note also that the path from vrefl to vss is isolated from the rest of digital ground until it approaches vss. figure 6. ground architecture for controller layout analog ground power ground digit al ground vss vrefl pwm ground the pwm ground is also isolated as a separate ground plane section until it approaches vss. this is most important i n systems that use optocouplers, since the current that flows through the pwm ground return will be higher than other digital return currents. if a two layer board is used, traces replace the ground planes that are shown in figure 6. the partitioning, however , remains the same. in addition to grounding, controllers benefit from attention to avoiding 9 0 degree angles, since there are generally a lot of high speed signals on the digital portion of the board. routing with 45 degree angles or curves minimizes unwanted reflections, which increases noise immunity .
AND9071/d http://onsemi.com 8 conclusion for the most part, the functional architecture of motor drives is much more straightforward than some of the techniques that are required to get them to work. these challenging aspects arise from high levels of both di/dt and dv/dt that produce many noise management issues. these are systems in which a fraction of a picofarad of stray capacitance in the wrong place, a ground connection that i s not carefully routed, or the absence of a functionally not so obvious component will all cause improper operation. the most important design issues are careful attention to grounding, minimizing critical loop areas, use of series bootstrap capacitors, careful attention to power transistor transition times, and filtering sensor inputs. additional benefits are gained by avoiding 90 degree angles in board layout and cancelling fields by routing equal and opposite current flows as close as possible to each other . as expected, consideration given to these issues up front pays of f when it comes to getting a design to work right the first time. o n semi conduct o r and are regist ered trademarks of semiconduct o r co mponent s indust r ies, llc (sci llc). sci llc owns the right s to a numb er of pat ent s, trademarks, copyright s, trade secret s, and ot her int e llect ual propert y . a list ing of sci llc? s product / pat ent coverage may be accessed at ww w . onsemi. com/ sit e/ pdf / p at ent ? m arking. pdf . sci llc reserves t h e r i ght t o m a ke c hanges w i t hout f u rt her n o t i ce t o a n y p r oduct s h e rein. s c i llc m a kes n o w a rrant y , r epresent at ion o r g uar ant ee r egar ding t h e s u it abilit y o f i t s p r oduct s f o r a n y par t i cular pur pose, nor does sci llc assume any liabilit y ar ising out of the applicat ion or use of any pr oduct or cir c uit , and s pecif ically disclaims any and all liabilit y , including wit hout limit at ion s pecial, c onsequent ial o r i n cident al d a mages. ? t ypical? p a ramet e rs w h ich m a y b e p r ovided i n s c i llc d a t a s heet s a nd/ or s pecif icat ions c a n a n d d o v a ry i n d i f f erent a pplicat ions and act ual perf ormance may vary over time. all operat ing parame ters, including ?t ypicals? must be validat ed for each cust omer applicat ion by cust omer ? s technical expert s . sci llc does n o t c onvey a n y l i cense under i t s p a t ent r i ght s n o r t h e r i ght s o f o t hers. s c i llc p r oduct s a r e n o t d e signed, i n t ended, o r a ut horized f o r u s e as c o mponent s in s yst ems int ended f o r surgical i m plant i n t o t h e b ody , o r o t her a pplicat ions i n t ended t o s upport o r s u st ain l i f e , o r f o r a n y o t her a pplicat ion i n w h ic h t h e f a ilure o f t h e s c i llc p r oduct c ould c r eat e a s i t uat ion w here personal i n jury o r d eat h m a y o ccur . s hould b u yer p u rchase o r u s e s c i llc p r oduct s f o r a n y s u ch u n int ended o r u naut horized appli cat i on, b u yer s hall i ndemnif y a n d h o ld sci llc a n d it s o f f i cer s , e m ployees, s ubsidiar i es, a f f iliat e s, a n d d i st r i but or s h a r m less a gainst a l l c l aims, c o st s, d a mages, a n d e x penses, a n d r easonable a t t o rney f ees a r ising o u t o f , d i rect ly o r i ndirect ly , any c l aim o f p e rsonal injury o r d eat h associat ed wit h s u ch unin t ended or u naut horized use, e v en if s u ch c l aim a lleges t hat s c i l lc was negligent r egarding the design or m anuf act u re of t h e part . sci llc is an equal opport unit y / a f f irmat i ve act i on employer . this lit e rat u re is subject t o all applicable copyrig ht laws and is not f o r resale in any manner . p ublica tion ordering informa tion n. american t echnical support : 800?282?9855 t oll free usa/canada europe, middle east and africa t echnical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 AND9071/d litera ture fulfillment : literature distribution center for on semiconductor p .o. box 5163, denver , colorado 80217 usa phone : 303?675?2175 or 800?344?3860 t oll free usa/canada fax : 303?675?2176 or 800?344?3867 t oll free usa/canada email : orderlit@onsemi.com on semiconductor w ebsite : www .onsemi.com order literature : http://www .onsemi.com/orderlit for additional information, please contact your loc al sales representative
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